a) Field of the Invention
The present invention relates to a method of manufacturing silicon semiconductor devices, and more particularly to a method of manufacturing semiconductor devices having silicide interconnects.
b) Description of the Related Art
Generally, in order to connect a conductive pattern formed on the surface of a semiconductor substrate to another contact area, the conductive pattern is covered with an insulating film and after a contact hole is formed through this insulating film, a wiring pattern is formed. Wiring for the connection between circuits or nodes at very short distances is called a local interconnect.
A local interconnect between a wiring pattern formed on a field oxide film and a diffusion region on the substrate surface can be formed without a process of forming an interlayer insulating film and a process of forming a contact hole. It is therefore very desirable from the viewpoint of forming micro semiconductor devices and simplifying processes.
FIGS. 9A to 9D are cross sectional views of a semiconductor substrate illustrating a method of forming local interconnects using self-aligned silicide (salicide) techniques disclosed in U.S. Pat. No. 4,873,204.
As shown in FIG. 9A, on the surface of a silicon substrate 100 a field oxide film 101 is formed which defines active regions 102A and 102B. In the active region 102A a MOSFET is formed having a source region 103AS, a drain region 103AD and a gate electrode 104A, and in the active region 102B another MOSFET is formed having a source region 103BS, a drain region 103BD and a gate electrode 104B. On the side walls of the gate electrodes 104A and 104B, side wall insulators 105A and 105B are formed. The gate electrodes 104A and 104B are extended in the direction vertical to the drawing sheet and formed also on the field oxide film.
A silicon wiring pattern 104C is formed on the field oxide film 101 at the left side of FIG. 9A and side wall insulators 105C are formed on the side walls thereof.
A titanium film 106 is deposited covering the whole surface of the substrate, and an amorphous silicon film 107 is formed on the titanium film 106.
As shown in FIG. 9B, the silicon film 107 is partially etched to form amorphous silicon patterns 107A and 107B. The silicon pattern 107A extends from the upper surface of the source region 103AS and over the field oxide film 101 to the upper surface of the silicon wiring pattern 104C. The silicon pattern 107B extends from the upper surface of the drain region 103AD and over the field oxide film 101 to the upper surface of the source region 103BS.
After the silicon oxide film 107 is patterned, the substrate 100 is heated.
As shown in FIG. 9C, the titanium film 106 and the silicon surface in contact with titanium are subject to silicidation reaction so that a silicide layer is formed. The silicon patterns 107A and 107B react with the titanium film 106 to form silicide layers 108A and 108B.
The upper surfaces of the silicon pattern 104C and gate electrodes 104A and 104B react with the titanium film 106 and are silicidized. The surfaces of the source regions 103AS and 103BS and drain regions 103AD and 103BD also react with the titanium film 106 and are silicidized.
As shown in FIG. 9D, an interlayer insulating film 109 is deposited on the whole surface of the substrate. A contact hole is formed through the interlayer insulating film 109 to expose the surface of the silicide layer 108B, and a metal wiring pattern 110 is formed.
With the local interconnect forming method illustrated in FIGS. 9A to 9D, semiconductor active regions in the surface layer of the silicon substrate can be connected to other contact areas without using contact holes. This method is therefore effective for making semiconductor integrated circuits highly dense.
With this conventional local interconnect forming method, at the process shown in FIG. 9B the regions, where the silicon patterns 107A and 107B are formed, are covered with a resist pattern to selectively etch the silicon film 107. After this etching, the resist pattern used as the mask is removed by ashing with plasma or by dissolution with acid-containing etchant.
During the resist removing process, the titanium film 106 is in an exposed state at the region not covered with the resist pattern. Therefore, the exposed titanium film 106 may be oxidized or sputtered and thinned by plasma. The damaged titanium film 106 may make the succeeding silicidation reaction be unable to form a silicide film of good quality and low resistance.
Although local interconnects using silicide techniques are very effective for forming micro semiconductor devices, it cannot be said that the techniques are sufficiently mature.